As semiconductor memory devices are required to have larger capacities and low electric powered, the elements are increasingly downsized. However, the development of the recent scaling increases the characteristics fluctuations of the transistors, which lowers the operational margin of the SRAM and consequently makes difficult the stable writing at low source voltages.
As a technique to assist the writing operation of the SRAM, the write assist circuit has been positively used. The write assist circuit is divided largely in two modes. One mode lowers the power voltage of the memory cell and weakens the latch effect of the memory cell to facilitate the inversion of the data, i.e., facilitate the writing. The other mode makes upon writing the potential of the bit line on the side of writing zero a negative voltage, thereby increasing the potential width of the bit line to facilitate the writing. In view of the requirement of lowering the operational voltage, the latter mode provides more merit.
The followings are examples of related: Japanese Laid-open Patent Publication No. 2007-004960; Japanese Laid-open Patent Publication No. 2009-295246; and Japanese Laid-open Patent Publication No. 2011-065727.
The mode of making upon a writing the voltage of the bit line on the side of writing zero a negative voltage shifts the potential of the bit line on the side of writing zero from 0 V to a negative voltage by the effect of the capacitor connected to the bit line on the side of writing zero. However, for this mode, it is necessary to add for each bit line a capacitor having substantially the same capacitance associated with the bit line to a usual write circuit, which unavoidably increases the area of the peripheral circuit. The control circuit which generates and applies a negative voltage must be also provided for each bit line, which is also a cause for increasing the area of the peripheral circuit.